Conventional frequency synthesizers generally include a phase-locked loop (PLL). A PLL is a device that generates an output frequency that is a function of a reference frequency. When implemented in a device such as a wireless transceiver, the output frequency of the PLL may change frequently. For example, the output frequency of the PLL changes at start-up and when changing channels. In each of these situations, it is desirable for the PLL to settle as quickly as possible on a desired output frequency. Further, in frequency hopping spread spectrum (FHSS) transceivers and in frequency division duplexing (FDD) transceivers, the output frequency of the PLL may change for each frequency hop or each transmission or reception burst. Thus, the PLL is required to have an even faster settling time in order to comply with the timing requirements of an FHSS or FDD transceiver. It is also desirable in many communication systems to accurately control the loop gain and loop bandwidth of the PLL so as to maximize tradeoffs between settling time and spectral noise or to accurately control the dynamic behavior of the PLL to match desired or predetermined characteristics of a communication signal path. The sensitivity or tuning gain of a controllable oscillator may vary with operating or environmental conditions or variations in the manufacturing process. Variations in the tuning gain may cause the loop gain of the PLL to vary, leading to undesirable variation in the noise spectrum and dynamic behavior of the PLL.
A controllable oscillator in the PLL system may use a tunable element with discrete steps, such as a selectable capacitor bank, for coarse tuning, and may use a continuously tunable element, such as one or more varactor diodes, for fine tuning. One PLL system starts with a coarse tuning mode for rapid frequency tuning before switching to a fine tuning mode for stabilization and final settling. Some frequency synthesizers in the prior art, such as those described in U.S. Pat. No. 6,724,265, provide for compensation of oscillator tuning gain by implementing a calibration technique wherein the controllable oscillator tuning voltage is measured when the controllable oscillator is phase locked to predetermined frequencies related to the desired final lock frequency. The time required for tuning gain compensation may comprise a significant portion of the total time allowed for the PLL to settle to the final desired lock frequency, increasing the duty cycle and power consumption of the PLL or in some cases preventing the PLL from meeting the required settle time of some communication systems. In addition, the prior art calibration techniques may require additional circuitry adding complexity and cost to the PLL. Thus, there is a need for a fast tuning calibration technique that requires little additional area and complexity in the PLL.